UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 5 Issue 1
January-2018
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1801322


Registration ID:
518989

Page Number

27-32

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Title

Compatible VLSI Architecture of Multiplier and Accumulator Based on Modified Booth Algorithm

Abstract

In our study, we propose the best solution to this problem by introducing a new efficient VLSI architecture of parallel Multiplier-and Accumulator (MAC) using hybrid approach for high-speed arithmetic operations. Since the accumulator that has the largest delay in MAC, the Carry Save Adder (CSA) and compressor techniques are used as one of the processing element to improve the overall performance. Since, the accumulator that has the largest delay in MAC was merged into CSA, hence the overall performance is elevated. The Proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme to improve the performance. like radix This study presents an efficient implementation of high speed multiplier, Radix-8 modified Booth multiplier algorithm. The parallel 2 and radix 4 modified booth multiplier does the computations using lesser adders and lesser iterative steps. However, the fact remains that the area and speed are two conflicting performance constraints. Hence, innovating increased speed always results in larger area. In this, we arrive at a better trade-off between the two, by realizing a marginally increased multipliers speed performance the proposed MAC will show the better properties to the existing standard design in many ways and performance twice as much as the previous research in the similar clock frequency.

Key Words

Booth Multiplier, Carry Save Adder–CSA, Computer Arithmetic, Digital Signal Processing-DSP, Multiplier & Accumulator-MAC, Booth Algorithm etc.

Cite This Article

"Compatible VLSI Architecture of Multiplier and Accumulator Based on Modified Booth Algorithm", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 1, page no.27-32, January-2018, Available :http://www.jetir.org/papers/JETIR1801322.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Compatible VLSI Architecture of Multiplier and Accumulator Based on Modified Booth Algorithm", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 1, page no. pp27-32, January-2018, Available at : http://www.jetir.org/papers/JETIR1801322.pdf

Publication Details

Published Paper ID: JETIR1801322
Registration ID: 518989
Published In: Volume 5 | Issue 1 | Year January-2018
DOI (Digital Object Identifier):
Page No: 27-32
Country: Jaipur, Rajasthan, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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