• Raghuveer Patel
• Dr. Namit Gupta

This Paper is devoted for the design and analysis of high speed multiplier. In this paper I have used three different techniques to Design high speed multiplier. In the first technique Array multiplier is designed to perform 8*8 multiplication, in second technique Wallancetree multiplier is designed to perform 8*8 multiplication and in the last technique Vedic mathematics is used to design an 8*8 multiplier. VHDL programs of all this multipliers are synthesized using Xilinx 9.2i software and simulated using Xilinx ISE simulator. The comparative study of different multipliers is done for finding the efficient multiplier design to perform high speed operation of multiplication and it has been found that the Vedic multiplier is more efficient than Array and Wallancetree multiplier because it gives minimum delay for multiplication. The designed Vedic multiplier is based on “Urdhva-tiryakbhyam” algorithm or sutra of ancient Indian Vedic mathematics. It is one of the sixteen sutras of Vedic mathematics. Vedic mathematics sutra “Urdhva-tiryakbhyam” increases the speed of multiplier by reducing the number of partial products. Hence the speed of overall system or processor can be increased by designing high speed Vedic multiplier.

VHDL, Multiplier, Array multiplier, Wallancetree multiplier, Vedic multiplier, Urdhva-tiryakbhyam sutra, SOP, POS, ISE

"DESIGN AND SIMULATION OF DIFFERENT TYPES OF MULTIPLIERS USING VHDL CODE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 5, page no.220-226, May-2018, Available :http://www.jetir.org/papers/JETIR1805043.pdf

"DESIGN AND SIMULATION OF DIFFERENT TYPES OF MULTIPLIERS USING VHDL CODE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 5, page no. pp220-226, May-2018, Available at : http://www.jetir.org/papers/JETIR1805043.pdf