• Aamir Bin Hamid
• Nadeem Tariq Beigh
• Ritu Singh

This paper presents a description of modified booth’s algorithm for multiplication two signed binary numbers. Radix-2 booth’s algorithm is explained, it is then identified that the main bottleneck in terms of speed of the multiplier is the addition of partial products. Radix-4 Booth’s algorithm is presented as an alternate solution, which can help reduce the number of partial products by a factor of 2.The booth’s multiplier is then coded in Verilog HDL, and area and timing analysis is performed on it. Radix-4 Booth’s multiplier is then changed the way it does the addition of partial products by utilizing a configuration register for range detection to reduce the number of partial product additions. Results of timing and area are then shown. The results table contain device utilization and timing results of 2 multipliers i.e. Radix-4 booth’s multiplier) and radix-4 modified booth’s multiplier with configuration register.

Booth’s multiplier, Radix-4, Xilinx, Multiplier, Verilog, Configuration Register, Optimization.

"RADIX-4 MODIFIED BOOTH’S MULTIPLIER USING VERILOG RTL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 5, page no.1072-1080, May-2018, Available :http://www.jetir.org/papers/JETIR1805369.pdf

"RADIX-4 MODIFIED BOOTH’S MULTIPLIER USING VERILOG RTL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 5, page no. pp1072-1080, May-2018, Available at : http://www.jetir.org/papers/JETIR1805369.pdf