UGC Approved Journal no 63975(19)
New UGC Peer-Reviewed Rules

ISSN: 2349-5162 | ESTD Year : 2014
Volume 12 | Issue 9 | September 2025

JETIREXPLORE- Search Thousands of research papers



WhatsApp Contact
Click Here

Published in:

Volume 5 Issue 6
June-2018
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

7.95 impact factor calculated by Google scholar

Unique Identifier

Published Paper ID:
JETIR1806145


Registration ID:
183161

Page Number

151-161

Share This Article


Jetir RMS

Title

Scalable approach for electricity hunch reduction in the course of test-primarily based good judgment BIST

Authors

Abstract

The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self-Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss. In this paper, we propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve target fault coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.5.

Key Words

Index Terms— Logic BIST (LBIST), microprocessor, power droop (PD), test.

Cite This Article

"Scalable approach for electricity hunch reduction in the course of test-primarily based good judgment BIST", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 6, page no.151-161, June-2018, Available :http://www.jetir.org/papers/JETIR1806145.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Scalable approach for electricity hunch reduction in the course of test-primarily based good judgment BIST", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 6, page no. pp151-161, June-2018, Available at : http://www.jetir.org/papers/JETIR1806145.pdf

Publication Details

Published Paper ID: JETIR1806145
Registration ID: 183161
Published In: Volume 5 | Issue 6 | Year June-2018
DOI (Digital Object Identifier):
Page No: 151-161
Country: vijayawada, Andhra Pradesh, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


Preview This Article


Downlaod

Click here for Article Preview

Download PDF

Downloads

0003076

Print This Page

Current Call For Paper

Jetir RMS