• M. Ayesha
• K .Murali

Data-driven clock gated (DDCG) and multibit flip-flops (MBFFs) are two low-power design systems that are normally treated freely. Merging these procedures into a single get-together algorithm and design stream empowers furthermore power speculation reserves. We contemplate MBFF assortment and its agreeable vitality with FF data-to-clock toggling probabilities. A probabilistic model is completed to extend the ordinary imperativeness speculation supports by get-together FFs in growing solicitation of their data-to-clock toggling probabilities. We show a front-end design stream, guided by physical configuration considerations for a 65-nm 32-bit MIPS and a 28-nm mechanical framework processor. It is seemed to achieve the power save assets of 23% and 17%, independently, stood out and designs from standard FFs. About part of the assets was a result of planning the DDCG into the MBFFs

Clock gating (CG), clock network synthesis, low-power design, multibit flip-flop (MBFF).

"DESIGN AND IMPLEMENTATION OF MULTIBIT FLIPFLOP USING COMBINATIONAL LOGIC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 6, page no.44-48, June-2018, Available :http://www.jetir.org/papers/JETIR1806507.pdf

"DESIGN AND IMPLEMENTATION OF MULTIBIT FLIPFLOP USING COMBINATIONAL LOGIC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 6, page no. pp44-48, June-2018, Available at : http://www.jetir.org/papers/JETIR1806507.pdf