• BATHINI SANDHYA RANI
• Mrs. MUNI PRAVEENA RELA
• DR. PRADEEP KUMAR

NOC (Network on Chip) has become the better communication system with bus based network for complex designs reducing problems in bandwidth, power dissipation etc. Like SoC, NOC is also tested for faults and defects.NOC testing involves testing of routers and router links. In NOC, part of area is occupied by routers which are in turn occupied by FIFO buffers and Buffer Logic. Run time faults in FIFO and Buffer logic are large compared to others component faults of NOC. Therefore, testing of NOC involves testing of FIFO and BUFFER LOGIC to ensure no faults and physical defects also. To avoid this, FIFO and routing logic is tested by transparent test algorithms targeting permanent FIFO faults. This algorithm is used for periodic testing of buffer at each location without effecting overall throughput of NOC except buffers This paper proposed Programmable MBIST for Efficient In-field testing of FIFO buffers in NOC’s. It gives the flexibility of choosing March algorithm after fabrication too. Proposed algorithm is based on on IEEE 1500 standard protocol. Area of BIST circuit can also be reduced as compared to BIST with dedicated hardware when applied to large number of BIST algorithms.

"PROGRAMMABLE MBIST DESIGN FOR EFFICIENT IN-FIELD TESTING OF FIFO BUFFERS IN NOC’S", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 7, page no.366-371, July-2018, Available :http://www.jetir.org/papers/JETIR1806558.pdf

"PROGRAMMABLE MBIST DESIGN FOR EFFICIENT IN-FIELD TESTING OF FIFO BUFFERS IN NOC’S", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 7, page no. pp366-371, July-2018, Available at : http://www.jetir.org/papers/JETIR1806558.pdf