• PALLAVI S pallavi S
• Swamy TN

In the early years this computer was stack architecture, later replaced by RISC architecture. Now the intent is to replace the hypothetical, emulated computer by a real one. This idea was made realistic by the advent of programmable hardware components called field programmable gate arrays (FPGA). The RISC-V Processor have reduced number of Instructions, fixed instruction length, more general purpose registers, load-store architecture and simplified addressing modes which makes individual instructions execute faster, achieve a net gain in performance and an overall simpler design with less silicon consumption. In this light, the choice of a RISC (Reduced Instruction Set Computer) is obvious. The use of an FPGA provides a substantial amount of freedom for design. Yet, the hardware designer must be much more aware of availability of resources and of limitations than the software developer. Also, timing is a concern that usually does not occur in software, but pops up unavoidably in circuit design. In this paper, development of a fully synthesizable 64-bit processor based on the open-source RISC-V (RV64I) ISA is presented. This processor is designed for targeting low cost embedded devices. The resulting processor is a single core, in-order, non-bus based, and RISC-V processor with low hardware complexity. The proposed processor is implemented in Verilog HDL and further prototyped on FPGA” Spartan 6” board. It is found that the maximum operating frequency is 57.007MHz. The power is estimated to be 0.037 W using Xilinx Power Analyzer.

RISC-V,5-Stage Pipelining, FPGA, Verilog HDL.

"SINGLE CYCLE 64-BIT RISC-V PROCESSOR AND IT’S FPGA PROTOTYPE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 8, page no.644-650, August-2018, Available :http://www.jetir.org/papers/JETIR1807555.pdf

"SINGLE CYCLE 64-BIT RISC-V PROCESSOR AND IT’S FPGA PROTOTYPE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 8, page no. pp644-650, August-2018, Available at : http://www.jetir.org/papers/JETIR1807555.pdf