• C. Teja Kumar
• K. Sravan Kumar

Arithmetic multipliers are the most difficult operational circuits. The entire operation of the circuits directly depends on the multiplier performance. When a p-channel MOS transistor device is in negative bias voltage ( −Vdd), the transistor device suffer with negative bias temperature instability effect due to this changes in threshold value of the MOS device, thereby decreases the speed of the multiplier. The positive bias temperature instability (PBTI) similar phenomenon takes place when an n channel MOS device is in positive bias voltage. Both the effects decreases the transistors speed in the multiplier circuit and also the entire system may incorrect because of timing violations in the long term. Hence, it is necessary to design the multipliers with higher performance at present technology. We implement a higher performance multiplier design by using an adaptive hold logic circuit (AHL) technique. This AHL multiplier can able to provide the higher performance through the variable latency design and this logic design has been applied to the bypassing multipliers. In Experimental results, the given proposed design of 16-bit adaptive column-bypass with carry look-ahead adder improve performance up to 44.8% and 6.9% compared to the normal column bypass multiplier without and with adaptive hold logic circuit in 90 nm technology.

PBTI, bypass multiplier, AHL, variable latency design

"Implementation of High Performance Multiplier with Adaptive Hold Logic", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 8, page no.661-665, August-2018, Available :http://www.jetir.org/papers/JETIR1808248.pdf

"Implementation of High Performance Multiplier with Adaptive Hold Logic", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 8, page no. pp661-665, August-2018, Available at : http://www.jetir.org/papers/JETIR1808248.pdf