• Surendra

The PLC is one in which the power pins and the power distribution networks of ICs are used for data communication as well as power delivery. PLC is used in order to reduce the number of input pins that an IC needs to couple the test data signals to each and every node. Hence to extract the test data signals from this power lines, so many receivers are in need at each and every nodes of the ICs or at places where we have to apply the test. For this purpose, PLC receivers are already design as the circuit complexity increases, the number of internal nodes increases proportionally, and individual internal nodes are less accessible due to the limited number of available I/O pins. To address the problem, we proposed power line communications (PLCs) at the IC level, specifically the dual use of power pins and power distribution networks for application/observation of test data as well as delivery of power. A PLC receiver presented in this paper intends to demonstrate the proof of concept, specifically the transmission of data through power lines. The main design objective of the proposed PLC receiver is the robust operation under variations and droops of the supply voltage rather than high data speed. The PLC receiver is designed and fabricated in CMOS 1-μm technology under a supply voltage of 1.2V.

Design-for-testability (DFT), PLC at ICs, PLC receiver, power line communications (PLCs).

"Energy and Delay Efficient of CMOS PLC Receiver Design for Low Power Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 9, page no.865-871, September-2018, Available :http://www.jetir.org/papers/JETIR1808426.pdf

"Energy and Delay Efficient of CMOS PLC Receiver Design for Low Power Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 9, page no. pp865-871, September-2018, Available at : http://www.jetir.org/papers/JETIR1808426.pdf