• Riya
• Amandeep Singh Bhandari

New technology innovation is facing a big challenge of miniaturization and low power electronics. Reversible logic proves to be an emerging solution. Reversible logic has various applications in modern low power computing environment. Adders play a major role in ALU and processors of any computing environment. Adders are not only suitable for addition but for subtraction and multiplication also. For many commercial applications, decimal arithmetic is highly demanding. The main aim of this paper is to design the improved reversible 4-bit & 8-bit full adder/subtraction circuit using Dual Key Gate (DKG) and Dual key Gate Pair (DKGP) gates that work singly as full adder/full subtraction are used to realize the basic building blocks of logic circuits. The reversible 4-bit & 8-bit full adder/subtraction circuit aresynthesized and simulated in VHDL language using EDA (ElectronicDesign Automation) tool-Xilinx ISE design suit14.2.

Low power CMOS, quantum computing, reversible logic gates, parallel adder/subtraction, power consumption.

"Design and Implementation of 8-Bit Low Power Parallel Adder/Subtractor Circuit Using Reversible Computing", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 8, page no.545-553, August-2018, Available :http://www.jetir.org/papers/JETIR1808719.pdf

"Design and Implementation of 8-Bit Low Power Parallel Adder/Subtractor Circuit Using Reversible Computing", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 8, page no. pp545-553, August-2018, Available at : http://www.jetir.org/papers/JETIR1808719.pdf