• Avula Lokesh Reddy

In this project the series of steps are followed in Place and Route to meet the desired constraints efficiently using a cadence encounter tool for a Design. Placing logic cells, clock tree building and routing are the main steps followed in Place and Route. During this process mainly focus is done on CTS building by varying variables in the specification file and clearing fan-out violations by using cloning of cells through TCL scripting after route stage. Optimization techniques are used to meet desired timing constraints in each step in the design flow.

flow, CTS, fan-out, TCL scripting.

"AN EFFICIENT PLACE AND ROUTE IN VLSI PHYSICAL DESIGN ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 8, page no.91-94, August-2018, Available :http://www.jetir.org/papers/JETIR1808761.pdf

"AN EFFICIENT PLACE AND ROUTE IN VLSI PHYSICAL DESIGN ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 8, page no. pp91-94, August-2018, Available at : http://www.jetir.org/papers/JETIR1808761.pdf