• V. Manikanta
• M.Adiseshaiah
• Dr.V.Thrimurthulu

On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multi core systems. FPGA block RAMs (BRAMs) offer speed advantages compared to LUT-based memory designs but a BRAM has only one read and one write port previously. Not only does the excessive demand on BRAMs block the usage of BRAMs from other parts of a design, but the complex routing between BRAMs and logic also limits the operating frequency. Designers need to use multiple BRAMs in order to create multi-port memory structures which are more difficult than designing with LUT-based multiport memories. Although memories with a large number of read and write ports are important, their high implementation cost means they are used sparingly in designs. As a result, FPGA vendors only provide dual-ported block RAMs to handle the majority of usage patterns. Multi-port memory designs increase overall performance but come with area cost. a brand new perspective and a more efficient way of using a conventional two reads one write (2R1W) memory as a 2R1W/4R memory. By exploiting the 2R1W/4R as the building block, previous approaches introduce a hierarchical design of 4R1W memory that requires fewer BRAMs than the previous approach of duplicating the 2R1W module. These methods used XOR based approaches, and gave us either single read multi write or multi read single write, our proposed method is giving multi write and multi read by hierarchical design of 2write and 2 read. Proposed system provided area and power efficient design compared to 2r/1w or 1r/2w along with this operating frequency also got enhanced.

FPGA, Multiport memory, BRAM.

"Segmented B-RAM Based Multiport Memory For Field Programmable Gate Array", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 11, page no.290-294, November-2018, Available :http://www.jetir.org/papers/JETIR1811338.pdf

"Segmented B-RAM Based Multiport Memory For Field Programmable Gate Array", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 11, page no. pp290-294, November-2018, Available at : http://www.jetir.org/papers/JETIR1811338.pdf