• RAJU KATRU
• Dr.M.Chandrasekher

Abstract— Soft faults pretence a constancy threat to recent electronic circuits. This makes defense in opposition to soft faults a prerequisite for many applications. For some applications, an interesting option is to use algorithmic-based fault tolerance (ABFT) techniques that try to utilize the algorithmic properties to detect and correct faults. Signal processing and communication applications are well matched for ABFT. One illustration is fast Fourier transforms (FFTs) that are a key building block in many systems. Several defense systems have been planned to detect and correct faults in FFTs. Among those, probably the exploit of the Parseval or sum of squares check is the most broadly known. In modern communication systems, it is more and more common to locate several blocks operating in parallel. in recent times, a technique that exploits this fact to execute fault tolerance on parallel filters has been planned. In this brief, this method is first applied to protect FFTs. Then, two enhanced protection systems that combine the use of fault correction codes and Parseval checks are planned and evaluated. The results show that the planned systems can further decrease the execution cost of protection.

Key words— Fault correction codes (ECCs), Fast Fourier Transforms (FFTs), Soft faults.

"Parallel Fast Fourier Transform with fault Tolerant realization on System on Chip", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 11, page no.491-498, November-2018, Available :http://www.jetir.org/papers/JETIR1811364.pdf

"Parallel Fast Fourier Transform with fault Tolerant realization on System on Chip", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 11, page no. pp491-498, November-2018, Available at : http://www.jetir.org/papers/JETIR1811364.pdf