• G.GANGAPRASASAD
• MANDAPATI RAJA

Abstract: Network-on-Chip (NoC) is a paradigm proposed to satisfy the communication demands of future Systems-on-Chip (SoC). Area and performance play a significant role since the size of technology to build modern digital systems are reduced. A router is the fundamental component of a NoC. In this paper, the Bidirectional Router using virtual channel regulator was designed and analyzed the various parameters such as area, speed and power. The Bidirectional router has consumed more area overhead, less speed and power. So the virtual channel regulator concept was implemented by logically combine virtual channel in BiNoC architecture, which dynamically allocates Virtual Channels (VC) and buffer resources according to network traffic conditions. The proposed architecture increases the speed of operation and reduces the critical path of the circuit. The aim of this work is to present a modified architecture of the BiNoC router to achieve higher area and speed efficiency using changes at the architecture level. The proposed architecture of BiNoC router is simulated in Xilinx ISE 9.1i software. The source code is written in VHDL. FPGA implementation of BiNoC Router has been performed on Xilinx Virtex2 FPGA. From the implementation results, the proposed router is operated with higher speed by 70%, area reduced by 8.47%.

Interconnection networks, on-chip communication, Reconfigurable, NoC, FPGA.

"AN INVESTIGATION AND PERFORMANCE EVALUATION OF VARIOUS ARBITRATION SCHEMES ON FPGA FOR NOC ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 11, page no.320-333, November-2018, Available :http://www.jetir.org/papers/JETIR1811446.pdf

"AN INVESTIGATION AND PERFORMANCE EVALUATION OF VARIOUS ARBITRATION SCHEMES ON FPGA FOR NOC ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 11, page no. pp320-333, November-2018, Available at : http://www.jetir.org/papers/JETIR1811446.pdf