• G. AKHILA
• V. PRADEEP KUMAR

This paper describes Improved Hamming Code, At whatever point data is stored or transmitted, some chance one or more bits will "flip" i.e., will change to an incorrect value. Such incorrect values are called errors; they may be because of a changeless shortcoming (broken hardware) or a transient condition. To neutralize this issue and guarantee dependable operation, error correcting codes (ECC) are utilized. Additional bits are sent or stored close by the data bits to give redundant data. With enough bits of deliberately picked redundant data, we can detect or correct the most likely classes of errors. Hamming code error correction is most generally utilized for computer memories. Hamming code with additional parity/redundancy bit can detect and correct single-bit errors and detect two bit errors. Hamming code is normally utilized for transmission of data with little lengths. Scaling it for bigger data lengths, results in a ton of overhead because of interspersing the redundancy bits and their evacuation later. Improved hamming code strategy is exceptionally adaptable without such overhead. Accordingly it is suitable for transmission of huge size data bit-streams with much lower overhead bits per data bit ratio. The project's objective is to design an error correction core utilizing improved hamming code. Hamming code with extra parity bit can detect and correct single-bit errors and detect two bit errors. The error correction core design endeavored in the paper utilizes improved hamming code error correction strategy. This strategy can detect and correct single-bit errors. In traditional hamming code strategy, extensive quantities of overhead bits are utilized as a part of the procedure of computation of parity/redundancy bits. In improved hamming code system the quantity of overhead bits is significantly decreased. The parity bits are annexed toward the end of data bits. This wipes out the overhead of interspersing the redundancy bits at the sender end and their evacuation at the receiver end. This work is accepted to serve as a decent error correction system for transmission of substantial size data bit-streams the length of there is probability of at the most single-bit error amid transmission.

Hamming Code, Error Correction.

"Module Design Approach of Hamming Code Using Advanced Verilog Concept of FPGA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 11, page no.81-86, November-2018, Available :http://www.jetir.org/papers/JETIR1811909.pdf

"Module Design Approach of Hamming Code Using Advanced Verilog Concept of FPGA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 11, page no. pp81-86, November-2018, Available at : http://www.jetir.org/papers/JETIR1811909.pdf