• Potti Chendi Alekya
• K.R.Surendra
• Dr.N.Pushpalatha
• Dr.Irala Suneetha

This work presents an implementation of Discrete Wavelet Transform (DWT)using Systolic architecture in VLSI .This architecture consist of Input delay unit, filter, register bank and control unit. This performs the calculation of high pass and low pass coefficients by using only one multiplier. This architecture has been simulated and implemented in VLSI. The hardware utilization efficiency is more compared to the referred due to FBRA Scheme. The systolic nature of this architecture corresponding to a clock speed of 115.9 MHz has its advantage in Optimizing area, time and power. The architecture is simple, modular, and cascadable for computation of one, or multi-dimensional DWT.

DWT, Six tap FIR Filter, Systolic Array Architecture, Decomposition, FBRA

"Efficient Systolic Architectures for Discrete Wavelet Transforms ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 12, page no.167-173, December-2018, Available :http://www.jetir.org/papers/JETIR1812222.pdf

"Efficient Systolic Architectures for Discrete Wavelet Transforms ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 12, page no. pp167-173, December-2018, Available at : http://www.jetir.org/papers/JETIR1812222.pdf