• Madhu Shakya
• Shweta Agrawal

Flip-flops (FF) are broadlyutilized to obtain&preserve data in preferredserieswhile recurring clock intervals for partial period of time adequate for another circuit within method. So rising speed &diminishing power of FF caused to raise total speed &diminish power of circuits. This paper purpose is Double Gate, High-Speed and low power design of CMOS D flip-flop using DG (Double Gate) FINFET (Fin shaped Field effect transistor) Technique. CMOS D flip flops are first preference to implement different type of binary counters, shift registers and analog and digital circuit system. In CMOS technology leakage power is primary significance. DG FINFET is the best option for the added control transistor. The authenticationoutputspecify that our optimization diminish power utilization by more than 50% at low data switching activity with an suitablelocation& setup time penalty compared with that of DG FINFET flip-flop. Both existing design and proposed design issimulated using Cadence tool at 90nm and 45nm technology.

CMOS, D-Flip Flop, Leakage Power, Leakage Current, Delay, Cadence

"Design and Simulation of Low Power CMOS D-Flip Flop using DG FINFET Techniques", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 12, page no.395-401, December-2018, Available :http://www.jetir.org/papers/JETIR1812453.pdf

"Design and Simulation of Low Power CMOS D-Flip Flop using DG FINFET Techniques", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 12, page no. pp395-401, December-2018, Available at : http://www.jetir.org/papers/JETIR1812453.pdf