• Rita Mahajan
• Sahibia Kaur Vohra
• Deepak Bagai

FIR (Finite Impulse Response) digital filters are the most important part of digital signal processing and is used widely in various applications like performing multiplications, complex computations and selecting desired frequency for various applications. FIR filters consist of multipliers, adders, delay units. FIR filters has been chosen as it offers more stability and easy implementation because of its finite length and no feedback in the circuit. However, the implementation of a large length Filter is still a challenging task. Making and implementing the circuit is not only the task as it is very important to check the correctness of the circuit and making the circuit more reliable. Further reliability of any circuit can be increased by making the circuit fault tolerant. Since FPGA is a programmable device and is prone to SEUs( Single event upsets) due to radiations therefore it is very important to make the implemented circuit on FPGA a fault tolerant. Fault injection can be done for that purpose and then we can check the reliability of the circuit. The MCM (Multiple Constant Multiplication) FIR filter is simulated and synthesized using Xilinx ISE 14.7. The filter is designed and programmed in Verilog HDL. MATLAB simulations are used to verify the results of the output of FIR filter.

Digital Filters, FIR, IIR, Fault Tolerance, CED, DMR.

"REVIEW ON FPGA IMPLEMENTATION OF FAULT TOLERANT FIR FILTER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 1, page no.33-39, January-2019, Available :http://www.jetir.org/papers/JETIR1901205.pdf

"REVIEW ON FPGA IMPLEMENTATION OF FAULT TOLERANT FIR FILTER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 1, page no. pp33-39, January-2019, Available at : http://www.jetir.org/papers/JETIR1901205.pdf