• S.ARIF BASHA
• N.SREENIVASA RAO

Low power and high speed adders are the most essential components of every contemporary signal processing application. Among the many adders, Carry Save Adder (CSA) is the high speed multi operand adder used in many applications. In the recent years, various effort has been made for reducing the area, power consumption of the components as well as for reducing the propagation delay of them, such as scaling and different topologies like pass transistor logic (PTL), Transmission gates etc. This paper presents the design of low power and high speed Carry Save Adder with reduced no. of transistors using Modified Gate Diffusion Input (MGDI) technique. This technique has been adopted from Gate Diffusion Input Technique (GDI) and is used achieve reduced power consumption, delay and area of digital circuits, while maintaining low complexity of logic design. This paper aims at designing of 4bit and 16 bit CSA using conventional CMOS, GDI and MGDI techniques. After various performance comparisons, it is stated that total power dissipation, propagation delay and transistor count are much smaller in MGDI technique than compared to CMOS and GDI technique.

Carry Save Adder, CMOS, Gate Diffusion input, Modified Gate Diffusion input

"Low Power Energy Efficient Carry Save Adder with MGDI Technique Using Tanner Tool", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 1, page no.710-718, January-2019, Available :http://www.jetir.org/papers/JETIR1901399.pdf

"Low Power Energy Efficient Carry Save Adder with MGDI Technique Using Tanner Tool", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 1, page no. pp710-718, January-2019, Available at : http://www.jetir.org/papers/JETIR1901399.pdf