• S ANITHA
• Ch.Hima Bindu
• B.Hemanth Kumar
• U.Ajay Krishna
• I.V.Nagaraju

This paper mainly concentrates on the use of Inter Integrated Circuit (I2c) by using the SYSTEM VERILOG and explains the construction of an environment which is used for verification and implementation of various test cases for this I2C Master Protocol. The trending techniques in fabrication unit showed a path in logical functioning of silicon die which making the verification process as most challenging one. Today many methodologies are required for the verification itself because it consumes seventy percent of the entire design process. One of the testing and verifying methodologies like UVM was introduced to create an environment which is used for verification and without interfacing with DUT.

Inter Integrated Circuit (I2C), Verification environment, System Verilog, DUT.

"VERIFICATION ENVIRONMENT FOR I2C MASTER PROTOCOL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 3, page no.549-554, March-2019, Available :http://www.jetir.org/papers/JETIR1903982.pdf

"VERIFICATION ENVIRONMENT FOR I2C MASTER PROTOCOL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 3, page no. pp549-554, March-2019, Available at : http://www.jetir.org/papers/JETIR1903982.pdf