• P.Gopal Naik
• MUDAVATH SIVAJI NAIK

Hybrid configurable logic block architectures for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction. Multiple hybrid configurable logic block architectures, both non fracturable and fracturable with varying MUX:LUT logic element ratios are evaluated across two benchmark suites using a custom tool flow consisting of Leg Up-HLS, Odin-II front-end synthesis, ABC logic synthesis and technology mapping, and VPR for packing, placement, routing, and architecture exploration. Technology mapping optimizations that target the proposed architectures are also implemented within ABC. Experimentally, A significant amount of 42% area overhead results due to inclusion of the MUX4. However, the overhead when estimated with respect to the router area reduces to 8% and still further to 2% when estimated with respect to the area of the entire MUX. This is because the mapping tables are synthesized by the registers and connections in slices of FPGAs. Having large mapping tables would not only occupy slices, but also introduce more complex decision logics and routing. With architecture-aware technology mapper optimizations in ABC, additional area is saved, post-place-and-route. For fracturable architectures, experiments show that only marginal gains are seen after place-and-route up to ~2%. For both non fracturable and fracturable architectures, we see minimal impact on timing performance for the architectures with best area-efficiency.

Field-programmable gate array (FPGA), hybrid complex logic block, multiplexer (MUX).

"IMPLEMENTATION OF FPGA LOGIC ARCHITECTURE BY USING HYBRID LUT/MULTIPLEXER ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 3, page no.166-170, March-2019, Available :http://www.jetir.org/papers/JETIR1903B28.pdf

"IMPLEMENTATION OF FPGA LOGIC ARCHITECTURE BY USING HYBRID LUT/MULTIPLEXER ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 3, page no. pp166-170, March-2019, Available at : http://www.jetir.org/papers/JETIR1903B28.pdf