• G.Srinivasarao
• Ch.Hima Bindu
• P.Sowjanya
• A.Meenakshi
• V.Sandhya

In this paper we are discussing about multiply accumulator architecture of high speed and energy efficientto cycle which supports all numbers. An efficient MAC design using 4:2 compressors is presented in this concept. The main objective of this project is it reduces power and delay time using 4:2 compressor is mainly applied to compress (or) reduces partialproducts. This product decreases the maximum o/p power delay. Further this project enhanced by Baugh-Wooley multiplier for latency improvement. The baugh-wooley multiplier does its multiplication in 2’s compliment form.

Multiply-Accumulate (MAC), Compressor, Multiplier, Baugh-wooley, Low power, Low Latency.

"LOW POWER COMPRESSOR STANDS ON MAC ARCHITECTURE FOR DSP FUNCTIONALITY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 3, page no.444-447, March-2019, Available :http://www.jetir.org/papers/JETIR1903E67.pdf

"LOW POWER COMPRESSOR STANDS ON MAC ARCHITECTURE FOR DSP FUNCTIONALITY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 3, page no. pp444-447, March-2019, Available at : http://www.jetir.org/papers/JETIR1903E67.pdf