• S. Girish Babu
• N. Sreenivasa Rao

Several FET-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (MOSFET) for computing applications. The foremost focus in this paper, is on arithmetic circuit design in carbon nanotube FET (CNTFET) technology. In particular, the approach is to develop a low-power and low-delay CNTFET based ternary full adder design. The proposed design is relies on unary operators of multi-valued logic. MVL decreases inter connection requirements and power consumption by realizing more data transmission. Efficient designs for primitives like ternary half-adder (HA) and full-adder are developed. The proposed circuits are examined using HSPICE simulator with the standard 32 nm CNTFET technology. The simulation result shows that the proposed design reduces the power consumption and delay compared to previous design.

CNTFET, delay, full adder, half adder, MVL, power consumption.

"Design of CNTFET Based Efficient Ternary Logic Full Adder ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 3, page no.478-484, March-2019, Available :http://www.jetir.org/papers/JETIR1903L65.pdf

"Design of CNTFET Based Efficient Ternary Logic Full Adder ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 3, page no. pp478-484, March-2019, Available at : http://www.jetir.org/papers/JETIR1903L65.pdf