• Kishore T
• Jayamani R
• Jaivignesh R
• Ajin R

Most of the digital devices use multipliers for their operation especially in digital signal applications. It helps to achieve a high data throughput in digital devices. Comparing to addition, multiplication process consumes a greater deal of time, consuming more amount of power and area and thus reduces the speed of the processor. Aging of transistors has a considerable effect on the performance of the multiplier. The effect of aging can be reduced by the use of over-design approaches, but it leads to inefficiency in area and power. Furthermore, the use of fixed latency design may lead to timing violations. To overcome this predicament, we use low power variable latency multiplier with Adaptive Hold Logic (AHL). Negative bias and positive bias temperature instability, both degrade the transistor speed, and the system may fail owing to timing violations. Hence, it becomes more important to design highly reliable multipliers with reduced area, delay and power consumption. The proposed architecture will be designed as a razor based Vedic multiplier design with novel adaptive hold logic (AHL) circuit which as high efficiency than the existing column bypass multiplier. The experimental results show that our proposed architecture with 32 x 32 aging aware multipliers is more efficient and has lesser latency.

Aging Aware, Adaptive hold logic, Latency, Bypassing, Reliable.

"Realization of Aging Aware Multiplier using Verilog HDL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.359-362, April-2019, Available :http://www.jetir.org/papers/JETIR1904251.pdf

"Realization of Aging Aware Multiplier using Verilog HDL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp359-362, April-2019, Available at : http://www.jetir.org/papers/JETIR1904251.pdf