• G.Siva Prasad
• L. Viharika
• M.Divya
• R.Nagaraju
• K.Seetaramaraju

In this modern era, many of the digital systems are error resilient which allows us to take the advantage of approximate computations. This makes the use of replacement of exact computing units by their counterparts. Approximate computing can also decrease the complexity at the designing levels with an increase in performance and power efficiency. Adders and multipliers are the basic buildings blocks of many digital applications. These blocks can be approximated in several ways. Research works are on the rise at many levels on approximate computing. Approximation at designing level is more advantageous as the modifications at this level much easier than the preceding levels. A method of designing an approximate multiplier with a novel structure introduced in 16-bit adder compressor is proposed. The 16-bit adder compressor (AC) is designed with 8-2 adder compressors in general. The 8-2 adder compressor is designed with 7-2 and 3-2 adder compressors and half adders. The existing and proposed multiplier is designed using Xilinx 14.7 in the frontend. The speed of proposed multiplier 55.44% increase compare to Existing Multiplier.

Approximate multipliers, 16-Bit AC, AC’s.

"DESIGN OF HIGH SPEED APPROXIMATE MULTIPLIER USING ADDER COMPRESSORS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.8-14, April-2019, Available :http://www.jetir.org/papers/JETIR1904502.pdf

"DESIGN OF HIGH SPEED APPROXIMATE MULTIPLIER USING ADDER COMPRESSORS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp8-14, April-2019, Available at : http://www.jetir.org/papers/JETIR1904502.pdf