• Chaudhari Priyanka
• Pinky Brahmbhatt

Security is very important parameter of today’s era. Today most concerned thing about communication includes looks into on security concern. At present most recognized cryptographic algorithm for encryption is Advance Encryption Standard. Advanced encryption standard is most important algorithm of cryptographic. AES is symmetric key algorithm which is used to encrypt (cipher text) and decrypt (plain text) the data. Previously Data Encryption Standard (DES) is used but it’s proved inadequate because of smaller key length. An AES takes an input block size of 128 bit. AES has three size of cryptographic key 128,196 and 256 bit. Basically, AES uses substitution and permutation operation. AES can be implemented by both software simulation and hardware simulation but as compared to software simulation hardware simulation has more merits like low area consumption and less time requirement. A huge amount of hardware required for implementation of Advanced Encryption standard because if it’s complex nature. The huge amount of hardware requirement makes AES very complex and burdensome. In this paper we implemented FPGA based AES algorithm. Xilinx _ISE 14.7 software is being used for simulating and to synthetize the VHDL code. Xilinx’s SPARTEN 6 FPGA is used for implementation. One application is developed for transferring the data from PC to FPGA.

AES, Encryption, Decryption, FPGA, Visual Basic, VHDL ,Different Key Length.

"Design of Advance Encryption Standard Using VHDL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.300-307, April-2019, Available :http://www.jetir.org/papers/JETIR1904846.pdf

"Design of Advance Encryption Standard Using VHDL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp300-307, April-2019, Available at : http://www.jetir.org/papers/JETIR1904846.pdf