• Sunitha K
• Nagesh K N
• H VenkateshKumar

An arithmetic and logic unit (ALU) is core component of the processor. The ALU performs different arithmetic and logic operations like addition, subtraction, multiplication, logical AND, OR on input operands and produces output. In applications like Digital Signal Processing and crypto graphical implementations, delay and power consumption are important parameters of consideration. In ALU using ripple carry adder and multiplier like Dadda multiplier, delay is more. The adder and multiplier circuits being the most important modules used by the arithmetic operations of an ALU the main focus of concern in this 8 bit ALU design is, addition done using Ladner Fischer Adder (LFA) and multiplication operation using folded tree architecture along with clock gating which decreases the delay by 20-25%.The synthesis and simulation of 8-bit ALU is performed by using Xilinx and output wave forms are observed using Xilinx ISE simulator and ModelSim.

ALU,Adder,Multiplier,Clock gating

"ALU Design and Simulation Using Folded Tree and Clock Gating", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.535-541, May-2019, Available :http://www.jetir.org/papers/JETIR1905F81.pdf

"ALU Design and Simulation Using Folded Tree and Clock Gating", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp535-541, May-2019, Available at : http://www.jetir.org/papers/JETIR1905F81.pdf