• SHAFEEK BASHEER
• ANEESH A
• AUSTINE CYRIAC
• LAIJU P JOY
• JISHNU K MOHANAN

Memory components have an important role in the modern electronics industry. The performance of modern electronic devices somewhat depends on the efficiency of the memory cells used in it. Most of the research and development teams looking on to the SRAM memory cell due to its unique capability to retain the data. The entrenchment of VLSI technology gives a new face to the electronics industry. By the uses of VLSI technology the size of the electronic devices are reduced thereby, the area consumption reduces and increases the density. While going for the smaller technology sizes power consumption is an important factor for today's technology. The technology size reduction leads to leakage power, it is becoming an important contributing factor in total power dissipation of the circuit. In order to understand the power dissipation issues in the CMOS technology, briefly gone through the main power dissipation factors. In order to overcome the power dissipation and the delay, a new 10T static random access memory cell with NMOS sleep transistor and transmission gate in 45nm technology is proposed using cadence® virtuoso® EDA tool. The performance of the memory cell is evaluated by considering its data stability and power consumption and also the delay of the cell during read, write and hold modes of operation. In order to compare the performance of the system, some conventional SRAM cells are needed. So implemented the conventional 6T, 7T, 8T and 9T SRAM cells in 45nm technology and also implemented the conventional 10T SRAM cell in 65nm technology and calculated the read, write and hold stability. Also calculated the power consumption of each of these cells during the write, read and hold operations. While comparing the proposed 10T SRAM cell(45nm) with the conventional 10T SRAM cell (65nm), the proposed design has 61.92% reduction in write power and 72.53% reduction in read power and also 66.17% reduction in hold power and also the proposed design has 33.51% reduction in write delay and 38.82% reduction in read delay.

NMOS sleep transistor, Pass-transistor, SRAM, Transmission Gates (TG), DRC (Design Rule Check), LVS (layout versus Schematic), cadence.

"Design and Analysis of a Low Power 10T SRAM Cell in 45nm CMOS Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.499-504, May-2019, Available :http://www.jetir.org/papers/JETIR1905L75.pdf

"Design and Analysis of a Low Power 10T SRAM Cell in 45nm CMOS Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp499-504, May-2019, Available at : http://www.jetir.org/papers/JETIR1905L75.pdf