UGC Approved Journal no 63975(19)

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Published in:

Volume 6 Issue 6
June-2019
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1906B83


Registration ID:
215615

Page Number

520-525

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Title

FeedForward FFT Hardware Architecture Based On Rotator Allocation Using Modified Booth Algorithm

Abstract

The Fast Fourier transform (FFT) is one of the most important algorithms in the field of Digital signal processing. It is used to calculate the Discrete Fourier transform (DFT) efficiently. In order to meet the high performance and real time requirements of modern applications, hardware designers have always tried to implement efficient architectures for the computation of the FFT. A new feedforward FFT hardware architectures based on rotator allocation is presented. It consists in finding an efficient distribution of FFT rotations that reduces the number of rotators and their complexity. Radix-2 feedforward architectures based on rotator allocation are presented along with MDC methodology. In rotators, general multipliers and general adders are used for implementation. The Booth algorithm consists of repeatedly adding one of two predetermined values to a product P and then performing an arithmetic shift to the right on P. The multiplier architecture consists of two architectures, i.e., Modified Booth and Booth algorithm. By the study of different multiplier architectures, we find that Modified Booth increases the speed because it reduces the partial products by half. Also, the delay in the multiplier can be reduced by using Wallace tree. The energy consumption of the Wallace Tree Multiplier is also lower than the Booth and the array. The characteristics of the two multipliers can be combined to produce a high-speed and low-power multiplier. The modified stand-alone multiplier consists of a modified recorder (MBR). MBR has two parts, i.e., Booth Encoder (BE) and Booth Selector (BS).

Key Words

Fast Fourier transform (FFT), discrete Fourier transform (DFT), a Modified recorder (MBR), Booth Encoder (BE), Butter fly unit (BU).

Cite This Article

"FeedForward FFT Hardware Architecture Based On Rotator Allocation Using Modified Booth Algorithm", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.520-525, June-2019, Available :http://www.jetir.org/papers/JETIR1906B83.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"FeedForward FFT Hardware Architecture Based On Rotator Allocation Using Modified Booth Algorithm", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp520-525, June-2019, Available at : http://www.jetir.org/papers/JETIR1906B83.pdf

Publication Details

Published Paper ID: JETIR1906B83
Registration ID: 215615
Published In: Volume 6 | Issue 6 | Year June-2019
DOI (Digital Object Identifier):
Page No: 520-525
Country: -, -, - .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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