• ADAVIPALLI DINESH
• Mr. P. MADHU KUMAR

This paper presents the design and implementation of a pipelined 16-bit RISC Processor. By optimizing the ALU circuit in RISC processor highly power efficient digital system can be achieved. The use of low power and high performance sub-blocks like adder and multiplier can reduce the total power dissipation of Reversible Vedic ALU. The various blocks embody the Fetch, Decode, Execute and Store result to implement 4 stage pipelining. In RISC processor we are designing the reversible Vedic ALU. The only load and store is used to communicate with data memory. RISC exploitation pipeline makes CPI as one and improves speed of execution. Verilog Language is used for coding purpose. The proposed architecture is then simulated using Modelsim.

"Design And Implementation of Pipelined Reversible Vedic RISC Processor", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.622-629, June-2019, Available :http://www.jetir.org/papers/JETIR1906F97.pdf

"Design And Implementation of Pipelined Reversible Vedic RISC Processor", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp622-629, June-2019, Available at : http://www.jetir.org/papers/JETIR1906F97.pdf