• Syeda Husna Saba

This paper presents mixed decimation multipath delay Commutator (M2DC) for radix 2^2 4 parallel Fast Fourier Transform. Generally, the algorithms used are either Decimation In Time (DIT) or Decimation In Frequency (DIF) FFT in which additional clocks are required for reordering input and output bits which increases latency. Hence the concept of mixed decimation i.e. integrating DIT and DIF is proposed for 16 points and the 4 parallel radix 2^2 feed forward (MDC) architecture is implemented which increases the throughput. Therefore the proposed work provides higher throughput and lower latency.

Mixed decimation, MDC , Feed forward, throughput and latency

"Mixed Decimation MDC Architecture For Radix 2^2 Parallel FFT", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.438-444, June 2019, Available :http://www.jetir.org/papers/JETIR1906O65.pdf

"Mixed Decimation MDC Architecture For Radix 2^2 Parallel FFT", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp438-444, June 2019, Available at : http://www.jetir.org/papers/JETIR1906O65.pdf