• CHHODAVADIYA PARTHKUMAR
• PROF. MANISHA PATEL

Aim of the work is to design and reduce the dynamic power consumption of low power 32 bits RISC core processor. The design is based on 5-stage pipelined MIPS architecture. This paper proposes the design for the low power RISC processor. It is having five stages pipelining which is designed using Verilog HDL. RISC processors have a unique feature called pipelining. Pipelining is used to make processor faster. In Pipelining instruction cycle is divided into parts so that more than one instruction can be operated in parallel. Proposed instructions are simulated using Xilinx ISE 14.7. The processor is synthesized using Spartan3e XILINX Tool.

FPGA, RISC, 5-Stage Pipeline, MIPS Instruction set Architecture

"DESIGN AND IMPLEMENTATION OF 32 BIT 5-STAGE PIPELINE RISC PROCESSOR USING VERILOG HDL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.23-29, June 2019, Available :http://www.jetir.org/papers/JETIR1906P05.pdf

"DESIGN AND IMPLEMENTATION OF 32 BIT 5-STAGE PIPELINE RISC PROCESSOR USING VERILOG HDL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp23-29, June 2019, Available at : http://www.jetir.org/papers/JETIR1906P05.pdf