• MONISHA H M
• MEGHASHREE A C

Nowadays, Increasing technology increases the amount of logic that can be placed in a silicon chip driving highly integrated SoC design development. Verification is the important part of SoC manufacturing ,it gives particular implementation and functionality to DUT for check whether it has achieved specification or not. In this Paper, AHB-Lite protocol subset of AHB which is a part of AMBA(Advanced Microprocessor Bus Architechture), is verified using Hardware Verification Langauge System Verilog Assertion(SVA). The AHB-Lite is the on-chip-interconnect which manages the functional block in SoC design and finds the presence of error/bug in the design by generating simulation result, coverage report and assertion report using QUESTA SIM tool.

SoC, AHB Lite, SVA(System Verilog Assertion ), coverage and assertion

"SYSTEM VERILOG ASSERTION BASED DESIGN AND VERIFICATION OF AHB-LITE PROTOCOL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.950-956, June 2019, Available :http://www.jetir.org/papers/JETIR1906S70.pdf

"SYSTEM VERILOG ASSERTION BASED DESIGN AND VERIFICATION OF AHB-LITE PROTOCOL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp950-956, June 2019, Available at : http://www.jetir.org/papers/JETIR1906S70.pdf