• MANASA THONTA
• K.P.MANI

This project introduces a set of techniques that, considering the dynamic streaming behavior of algorithms, can achieve power savings by selectively switching off parts of the circuits when they are temporarily inactive. The techniques being independent from the semantic of the application can be applied to any application and can be integrated into the synthesis stage of a high-level dataflow design flow. This concept describes an approach for developing energy optimized run-time reconfigurable designs which benefit from clock gating. Field Programmable Gate Arrays FPGAs are highly desirable for implementation of digital systems due to their flexibility, programmability and low end product life cycle. The goal is to reduce the power consumption without sacrificing much performance or incurring a large chip area so that the territories of FPGAs applications can expand more effectively. Reducing the power of FPGAs is the key to lowering packaging and cooling costs, improving device reliability, and opening the door to new markets such as mobile electronics. Further, this project is enhanced by using modified clock gating technique with c elements and double edge triggered flipflops to further reduce power consumption.

Clock gating, Reconfigurable, Field Programmable Gate Arrays, Reliability, Flip-flop power optimization.

"ENERGY EFFICIENT RECONFIGURABLE APPLICATIONS USING MODIFIED CLOCK GATING", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.972-984, June 2019, Available :http://www.jetir.org/papers/JETIR1906S73.pdf

"ENERGY EFFICIENT RECONFIGURABLE APPLICATIONS USING MODIFIED CLOCK GATING", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp972-984, June 2019, Available at : http://www.jetir.org/papers/JETIR1906S73.pdf