• A. Phanimadhuri
• J. Priyanka

Abstract: In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible Full Adder/Subtractor with Design I, and Design II are proposed. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. The reversible full adders are placed in the DMFA. In this paper a modified 8-bit reconfigurable CLA block is presented. The proposed system gives the best performance compared to the previous systems.

"AN IMPROVED DESIGN OF APPROXIMATE ARITHMETIC UNITS USING REVERSIBLE LOGIC GATES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.377-383, June 2019, Available :http://www.jetir.org/papers/JETIR1906U86.pdf

"AN IMPROVED DESIGN OF APPROXIMATE ARITHMETIC UNITS USING REVERSIBLE LOGIC GATES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp377-383, June 2019, Available at : http://www.jetir.org/papers/JETIR1906U86.pdf