• Divya Srivastava
• Krishna Raj

A Fast Fourier transform architectural processor, will shows the significant effect for the performance of various communication-based subsystems. The FFT function can be pinned down to be consisting of consecutive multiplication and arithmetic adder operations for the complex numbers system representation, which is cited as the butterfly architectural units. The paper deals with the implementation of the floating-point arithmetic number architecture to the FFT system processor architecture, the focus is done mainly on the butterfly architectural units. The implementation of the FFT in FP number system makes the general-purpose processor get rid of the FP overhead of scaling and overflow. As the FP butterfly architectural unit gets beaten by its successor fixed-point butterfly unit on the terms of the computational delay offered, an optimum architecture of the FP butterfly unit could turn into a faster unit using the different number system approach that will help the system to do the faster computation in a fixed duration of time. A carry limited hybridized signed digit adder is proposed in the floating-point adder unit. The simulated result shows that the proposed architecture is faster in computation and have a less delay approach. In this paper, the analysis the gate delay, area and power consumption are done using the using Xilinx 14.2.

Floating-point(FP),FFT, Hybrid signed digits.

"Floating-Point Butterfly Architecture Representation using Hybrid Number Representation", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.435-441, June 2019, Available :http://www.jetir.org/papers/JETIR1906U95.pdf

"Floating-Point Butterfly Architecture Representation using Hybrid Number Representation", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp435-441, June 2019, Available at : http://www.jetir.org/papers/JETIR1906U95.pdf