• BATTULA SESHA SOWJANYA
• DR.I.SANTHI PRABHA

In the SoC quantity, validation is major part in chip manufacturing. Verification describes with the definite execution and functionality of design under test (DUT) and check that exact designations meet or not. The AHB LITE protocol is validated according to the model. First, the architecture of AHB Lite is done using single master and multiple slaves in Verilog language and simulates the design by using QuestaSim and the validation of protocol is done with assertions and also the functional verification is done with coverages.

AHB-LITE,AMBA,ASSERTIONS,COVERAGE

"SOC LEVEL DESIGN AND VERIFICATION OF AMBA-AHB PROTOCOL USING SYSTEM VERILOG", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.754-758, June 2019, Available :http://www.jetir.org/papers/JETIR1906Y35.pdf

"SOC LEVEL DESIGN AND VERIFICATION OF AMBA-AHB PROTOCOL USING SYSTEM VERILOG", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp754-758, June 2019, Available at : http://www.jetir.org/papers/JETIR1906Y35.pdf