• RAKURTHI CHITTI SAISRI
• GANTA NAGA LAKSHMI

Testing semiconductor memories is increasingly important today because of the high density of current memory chips. Most of the System-on-Chip (SoC) area covered by embedded memories. As these memories are very tightly integrated, consists majority of defects in soc. Detection of such a complex and diverse faults during fabrication is not possible. Hence leads to failure of soc in field. Usage of test algorithms may increase the coverage of complex faults, but unexpected failures can’t be covered by these algorithm. Providing possibility of choosing testing algorithms before using in SoC is very important. Programmable BIST approaches, allowing selecting after fabrication a large variety of memory tests, are therefore desirable, but may lead on unacceptable area cost. In this paper we investigate on the various functional fault models present for today’s memory technology and discuss about the ways and means to detect these faults. This project presents an effective architecture of MBIST for SRAM type with different configurations is proposed for not only ensuring high ability of detecting memory faults supported by the most popular algorithms namely MARCH C- and TLAPNPSF. Besides, architecture with dynamic configuration of highest address parameter and the state machine design enables to reach the wide range of memory depth. To ensure all fault cases and all configurations are covered, an automatically verification environment is designed to make progress conveniently. Further this project is enhanced by using clock gating technique for further improvement of power. Clock gating technique is applied to ring counter to select the addresses with sophisticated mechanism. Here, the concept involved in clock gating technique is providing power supply to the block; in which that selected row is presented. No supply will be provided to the non-accessed rows.

LOW POWER CLOCK GATING TECHNIQUE BASED MBIST DESIGN

"LOW POWER CLOCK GATING TECHNIQUE BASED MBIST DESIGN", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.78-82, June 2019, Available :http://www.jetir.org/papers/JETIR1907009.pdf

"LOW POWER CLOCK GATING TECHNIQUE BASED MBIST DESIGN", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp78-82, June 2019, Available at : http://www.jetir.org/papers/JETIR1907009.pdf