• Sarita Kumari
• Prof. Deepti malviya

This work proposes a simple and efficient Montgomery multiplication algorithm such that the low-cost and high-performance Montgomery modular multiplier can be implemented accordingly. The proposed Montgomery modular multiplier receives and outputs the data with binary representation and uses only one-level carry-save adder (CSA) to avoid the carry propagation at each addition operation. Experimental results show that the proposed Montgomery modular multiplier can achieve higher performance and significant area time product improvement when compared with previous designs.

Montgomery, Modular, VLSI, Cryptosystem

"Design and Performance Analysis of Montgomery Modular Multiplication VLSI Architecture", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.871-875, June 2019, Available :http://www.jetir.org/papers/JETIR1907121.pdf

"Design and Performance Analysis of Montgomery Modular Multiplication VLSI Architecture", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp871-875, June 2019, Available at : http://www.jetir.org/papers/JETIR1907121.pdf