• Iffath Zeba
• Ayesha Naaz

: Efficient FFT processor plays a very important role in the advanced communication systems. The demand for such processors increases heaps of times if “flexibility” is the added property. This work proposes a flexible FFT processor that supports five modes, designed and implemented using hardware-efficient folded FFT architecture. The proposed work is modeled in verilog VHDL and is implemented on Artix-7(xc7a100tfqq484-3) FPGA using Xilinx VIVADO system Design suite 2014.2. The proposed folded FFT processor consumes 20.56% less area when compared with parallel FFT processor designed and implemented in the same environment. Furthermore, there is still 3% reduction in area consumed when modified-booth multiplier is incorporated in the proposed design.

Variable-length, Fast Fourier Transform, Folded, Parallel.

"An Efficient Design Of Variable-length FFT processor using Folding Transformation", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.575-581, June 2019, Available :http://www.jetir.org/papers/JETIR1907225.pdf

"An Efficient Design Of Variable-length FFT processor using Folding Transformation", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp575-581, June 2019, Available at : http://www.jetir.org/papers/JETIR1907225.pdf