• Hemanshi Chugh

This paper presents the detailed study of four different multiplier architectures based on Vedic Multiplier, Booth encoded Wallace tree multiplier, Baugh Wooley multiplier and Braun multiplier. Here these architectures are implemented for 4, 8 bits. All the multipliers are coded in Verilog HDL and simulated in Model SIM and implemented on Xilinx Spartan 3E FPGA board. All multipliers are then compared for their performance based on LUTs and path delays. Furthermore, some modifications to speed up the overall multiplier architecture are also presented in this report. Results show that in case of signed multipliers Baugh Wooley gives better results as compared to Booth encoded Wallace tree. And in case of unsigned multipliers, Braun multiplier using carry skip adder shows better results than Vedic multiplier.

Vedic Multiplier, Booth encoded Wallace tree multiplier, Baugh Wooley multiplier, Braun multiplier

"Designing of Various types of multipliers and their implementation on FPGA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.1066-1070, June 2019, Available :http://www.jetir.org/papers/JETIR1907748.pdf

"Designing of Various types of multipliers and their implementation on FPGA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp1066-1070, June 2019, Available at : http://www.jetir.org/papers/JETIR1907748.pdf