• Harika G

Approximate arithmetic has become a prominent choice for applications tolerating inaccurate results. By relaxing accuracy requirements, circuit complexity, delay, and energy consumption can be significantly reduced. In this paper, an approximate parallel multiplier design, based on simplified logic is being proposed by us. This is carried out by calculating product terms, then compressing the adjacent bits of same column based on the required cluster depths and thereby mapping the resulting product terms to achieve a less number of product rows. Thus, a reduction in silicon area is expected to be achieved. Multipliers with varying bit widths viz., 8-bit, 16-bit and 32-bit are designed using Verilog. Post-simulation results done using Xilinx ISE 12.1 tool, show that nearly 50% reduction in silicon area could be achieved compared to accurate multiplier design. These multipliers could be used in power-constrained computing, multimedia applications, scientific computing etc.

approximate arithmetic, cluster depth, power-constrained computing

"A 32-Bit Area-Efficient Approximate Parallel Multiplier Design", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.143-146, June 2019, Available :http://www.jetir.org/papers/JETIR1907B83.pdf

"A 32-Bit Area-Efficient Approximate Parallel Multiplier Design", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp143-146, June 2019, Available at : http://www.jetir.org/papers/JETIR1907B83.pdf