UGC Approved Journal no 63975(19)

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Published in:

Volume 6 Issue 6
June-2019
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1907C14


Registration ID:
221418

Page Number

369-375

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Title

LOW REGIONAL IMPLEMENTATION AND COMPLEXITY OF 32-POINT 2-DCT HEVC BASED ON INTEGER FUNCTION

Abstract

Approximation of discrete cosine transform (DCT) is useful for reducing its computational complexity without significant impact on its coding performance. Most of the existing algorithms for approximation of the DCT target only the DCT of small transform lengths, and some of them are non-orthogonal. This paper presents a generalized recursive algorithm to obtain orthogonal approximation of DCT where an approximate DCT of length could be derived from a pair of DCTs of length at the cost of additions for input preprocessing. We perform recursive sparse matrix decomposition and make use of the symmetries of DCT basis vectors for deriving the proposed approximation algorithm. The algorithm is highly scalable for hardware as well as software implementation of DCT of higher lengths, and it can make use of the existing approximation of 8-point DCT to obtain approximate DCT of any power of two length,.We demonstrate that the proposed approximation of DCT provides comparable or better image and video compression performance than the existing approximation methods. It is shown that proposed algorithm involves lower arithmetic complexity compared with the other existing approximation algorithms. We have presented a fully scalable reconfigurable parallel architecture for the computation of approximate DCT based on the proposed algorithm. One uniquely interesting feature of the proposed design is that it could be configured for the computation of a 32-point DCT or for parallel computation of two 16-point DCTs or four 8-point DCTs with a marginal control overhead. The existing architecture uses a RCA (ripple carry adder) for the addition operation. The proposed architecture is found to offer many advantages in terms of hardware complexity, regularity and modularity by using advanced adder then the existing adder circuit. This paper proposes a high speed CARRY SELECT ADDER instead of RCA that requires much time to produce outputs. Experimental results obtained from FPGA implementation show the advantage of the proposed method.

Key Words

DCT, recursive algorithm, XILINX, VERILOG.

Cite This Article

"LOW REGIONAL IMPLEMENTATION AND COMPLEXITY OF 32-POINT 2-DCT HEVC BASED ON INTEGER FUNCTION", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.369-375, June 2019, Available :http://www.jetir.org/papers/JETIR1907C14.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"LOW REGIONAL IMPLEMENTATION AND COMPLEXITY OF 32-POINT 2-DCT HEVC BASED ON INTEGER FUNCTION", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp369-375, June 2019, Available at : http://www.jetir.org/papers/JETIR1907C14.pdf

Publication Details

Published Paper ID: JETIR1907C14
Registration ID: 221418
Published In: Volume 6 | Issue 6 | Year June-2019
DOI (Digital Object Identifier):
Page No: 369-375
Country: -, -, - .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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