UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
Call for Paper
Volume 11 | Issue 5 | May 2024

JETIREXPLORE- Search Thousands of research papers



WhatsApp Contact
Click Here

Published in:

Volume 6 Issue 6
June-2019
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

7.95 impact factor calculated by Google scholar

Unique Identifier

Published Paper ID:
JETIR1907P56


Registration ID:
223743

Page Number

387-392

Share This Article


Jetir RMS

Title

ENHANCED FAULT TOLERANT PARALLEL FFTS USING ERROR CORRECTION CODES AND PARSEVAL CHECKS USING ANCIENT VEDIC SUTRA

Abstract

Every year the complexity of communication systems and signal processing circuits will increase. This can be done by the CMOS technology scaling that allows the integration of too many transistors on a single device. This improved complexity will leads to failure of circuits. Identically, the transistors will run with low supply and are leads to errors due to noise and variations in the manufacturing. Hence, soft errors also increase as technology scaling increases. A soft error alters the actual value of the system which will disturb the electronic circuits operation. In order to overcome such situation, the best choice is to utilize Algorithmic-Based Fault Tolerance (ABFT) techniques for some applications. ABFT use algorithmic properties to locate and correct errors. ABFT technique is suitable for communication and signal processing applications. Fast Fourier Transforms (FFTs) is one of the examples which are major building blocks in many systems. To locate and correct errors in FFTs, many protection schemes have been proposed. Those protection schemes are Error Correction Codes and Parseval or Sum of Square (SOS) checks. These techniques are first applied to protect FFTs. Then by combining both error correction codes and Parseval or SOS checks a new improved protection scheme have been proposed and evaluated. The proposed scheme results in reduced computational time and implementation cost of protection.

Key Words

Error correction codes (ECCs), SOS checks, FFTs, Vedic multiplier, soft errors.

Cite This Article

"ENHANCED FAULT TOLERANT PARALLEL FFTS USING ERROR CORRECTION CODES AND PARSEVAL CHECKS USING ANCIENT VEDIC SUTRA ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.387-392, June 2019, Available :http://www.jetir.org/papers/JETIR1907P56.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"ENHANCED FAULT TOLERANT PARALLEL FFTS USING ERROR CORRECTION CODES AND PARSEVAL CHECKS USING ANCIENT VEDIC SUTRA ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp387-392, June 2019, Available at : http://www.jetir.org/papers/JETIR1907P56.pdf

Publication Details

Published Paper ID: JETIR1907P56
Registration ID: 223743
Published In: Volume 6 | Issue 6 | Year June-2019
DOI (Digital Object Identifier):
Page No: 387-392
Country: -, -, - .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


Preview This Article


Downlaod

Click here for Article Preview

Download PDF

Downloads

0002812

Print This Page

Current Call For Paper

Jetir RMS