• Mohammad Nasiruddin
• Dr. Prashant S. Sharma
• Dr. Vijay S. Chourasia

As the technology is expanding its scale from micro scale to nano scale. At such scale a new field is emerged called quantum computing. Quantum computing is based on the principle of reversible operation, in which the information is conversed and performs certain task in nanosecond. In order to implement a high speed multiplier a Vedic algorithm can be applied, because it perform simple operation and yield result quickly. The multiplication process involves two step generation of partial product and addition of partial product, these two steps are concurrently perform by the Urdhva Tiryakbhyam algorithm of Vedic Mathematics. The Multiplier and Accumulator (MAC) are the necessary elements of the digital signal processing like filtering, convolution, and transformations etc. Power consumption is recognized as a critical parameter in modern technology. The objective of a good multiplier is to provide a physically compact, high speed and low power consuming chip. First, we introduce the concept of Vedic Multiplier. Then, we implement a 16-bit MAC unit with Vedic multiplier and full pipelined accumulator using Urdhva Tiryakbhyam algorithm. We also compare the results with MAC unit implemented by other Vedic algorithms.

Adders, MAC Unit, Vedic Multiplier, Urdhva Tiryakbhyam algorithm, Xilinx

"IMPLEMENTATION OF OPTIMISED 16-BIT MULTIPLIER-ACCUMULATOR (MAC) UNIT WITH VEDIC MULTIPLIER AND FULL PIPELINED ACCUMULATOR", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.448-453, June-2019, Available :http://www.jetir.org/papers/JETIR1907T34.pdf

"IMPLEMENTATION OF OPTIMISED 16-BIT MULTIPLIER-ACCUMULATOR (MAC) UNIT WITH VEDIC MULTIPLIER AND FULL PIPELINED ACCUMULATOR", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp448-453, June-2019, Available at : http://www.jetir.org/papers/JETIR1907T34.pdf