• Swati Agrawal
• Dr.Shanti Rathore

Many techniques have been introduced to minimize the power consumption of new VLSI systems. However, most of these methods focus on the power consumption during normal mode operation (functional operation), whilst test mode operation has not normally been a predominant concern. However, it has been found that the power consumed during test mode operation is often much higher than normal mode operation because of the high switching activity in the nodes of the CUT during test. A novel technique that improves the power consumption during test with minimum effect in test length, fault coverage, or hardware area overhead is introduced here. The technique uses changing the design of LFSR that generates test pattern to be in correlation so that switching activity is reduced which will minimize power dissipation.

LFSR,BIST

"Design of LFSR using Pass transistor for Low Power BIST applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.714-719, June 2019, Available :http://www.jetir.org/papers/JETIR1908106.pdf

"Design of LFSR using Pass transistor for Low Power BIST applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp714-719, June 2019, Available at : http://www.jetir.org/papers/JETIR1908106.pdf