UGC Approved Journal no 63975(19)

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Published in:

Volume 6 Issue 6
June-2019
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1908150


Registration ID:
225448

Page Number

5-10

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Title

A Verilog Implementation of Built in Self Test with Linear Feedback Shift Register for Performance Improvement

Abstract

Built-in Self Test, or BIST, is the technique of designing additional hardware and software features into integrated circuits to allow them to perform self-testing. A linear-feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. Field programmable gate array (FPGA) has become widely accepted design approach for low- and medium-range application because of functional flexibility and low development cost. The role of testing is to detect whether something went wrong and the role of diagnosis is to determine exactly what went wrong. This work proposes an implementation of built in self test using verilog coding on xilnx 14.7 software. In this work, also implement Linear Feedback Shift Register and SRAM controller to support BIST for performance improvement.

Key Words

BIST, LFSR, SRAM, Controller, Latency, Area, High Speed, Low Power, Frequency

Cite This Article

"A Verilog Implementation of Built in Self Test with Linear Feedback Shift Register for Performance Improvement ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.5-10, June 2019, Available :http://www.jetir.org/papers/JETIR1908150.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"A Verilog Implementation of Built in Self Test with Linear Feedback Shift Register for Performance Improvement ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp5-10, June 2019, Available at : http://www.jetir.org/papers/JETIR1908150.pdf

Publication Details

Published Paper ID: JETIR1908150
Registration ID: 225448
Published In: Volume 6 | Issue 6 | Year June-2019
DOI (Digital Object Identifier):
Page No: 5-10
Country: Bhopal, Madhya Pradesh, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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