• Satish kumar
• Dr. Bharti Chourasia

Multiplication is a key operation to perform the processing speed of digital processor. Montgomery multiplication is a strategy for performing quick modular multiplication. This paper presents an outline on execution of Montgomery measured duplication estimation utilizing VLSI design. The Montgomery figuring is a fast particular increase procedure as regularly as conceivable used in cryptographic applications, in which the capability of cryptosystem depends upon the speed of secluded duplication. This audit gives the assessment between different adjustments done in Montgomery particular augmentation.

Multiplier, Montgomery, Modular, VLSI, Cryptosystem

"VLSI ARCHITECTURE OF MONTGOMERY MODULAR MULTIPLIER : A REVIEW", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.79-82, June-2019, Available :http://www.jetir.org/papers/JETIR1908C13.pdf

"VLSI ARCHITECTURE OF MONTGOMERY MODULAR MULTIPLIER : A REVIEW", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp79-82, June-2019, Available at : http://www.jetir.org/papers/JETIR1908C13.pdf