• O.P.P.Vardhanam
• T.Sahithi
• B.Sairam
• M.Srikanth Reddy
• G.V.Vinod

A mixed-logic design technique for line decoders,combining transmission gate logic, pass transistor dual-value logic and static complementary metal oxide semiconductors by this paper.Two novel topologies provided for the 2-4 decoder: a 14-transistor topology aiming on minimizing transistor depend and energy dissipation and a 15-transistor topology aiming on high power optimization.Both a traditional and an inverting decoder are applied in each case,yielding a total of four new designs.Furthermore,4 new 4-16 decoders are designed,by using mixed-logic 2-4 pre-decoders combined with general CMOS post-decoder.All proposed decoders have complete swinging functionality and reduced transistor rely as compared to their traditional CMOS counterparts.Finally,quite a few comparative spice simulations on the 32 nm shows that the proposed circuits present a enormous development in power and put off,outperforming CMOS in nearly all cases

Line decoders,Mixed -logic, High strength put-off performance.

"Design of Low Power High Performance 2-4 and 4-16 mixed logic line decoders", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 5, page no.500-509, May-2020, Available :http://www.jetir.org/papers/JETIR2005076.pdf

"Design of Low Power High Performance 2-4 and 4-16 mixed logic line decoders", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 5, page no. pp500-509, May-2020, Available at : http://www.jetir.org/papers/JETIR2005076.pdf