• Maneesh Pawar
• Dr. Anshuj Jain

Cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. Fastest data transmission with high accuracy is needed rapidly. Error detection and correction is important step during data transmission. There are various algorithm is capable to perform such task. This paper proposed a design and implementation of Cyclic Redundancy check-16 bit. Further the performance improvement is done through the proposed design in terms of reduced area, reduced latency and improved throughput.

CRC, Error, Correction, Speed, Power, Latency

"FPGA Implementation of Cyclic Redundancy Check-16 Bit using Pipelining Architecture Approach", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 1, page no.279-283, January-2021, Available :http://www.jetir.org/papers/JETIR2101240.pdf

"FPGA Implementation of Cyclic Redundancy Check-16 Bit using Pipelining Architecture Approach", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 1, page no. pp279-283, January-2021, Available at : http://www.jetir.org/papers/JETIR2101240.pdf